ERASE METHOD IN THIN FILM NONVOLATILE MEMORY
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United States of America Patent
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N/A
Issued Date -
Mar 26, 2009
app pub date -
Sep 16, 2008
filing date -
Sep 21, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any source-to-body short; (b) flexible erase which erases any number of memory cells in a block (i.e., from none to all cells); (c) source voltage may be set to optimize non-selected string channel boosting; and (d) the thickness of the thin-film device's body can be optimized for scalability. The method uses the access devices of the dual-gate memory cells in a memory string to form inversion channels, so as to provide conductive paths between the memory cells to be erased and a node at a more positive voltage than the erase voltage applied to the gate electrodes of the memory devices to be erased.

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- 15 United States
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SCHILTRON CORPORATION | 1638 CORNELL DRIVE MOUNTAIN VIEW CA 94040 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Walker, Andrew J | Mountain View, US | 106 | 5890 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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