Multiple chips bonded to packaging structure with low noise and multiple selectable functions
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United States of America Patent
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app pub date -
Nov 12, 2008
filing date -
May 19, 2000
priority date (Note) -
Abandoned
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Abstract
The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.
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