ESD PROTECTION CIRCUITS FOR MIXED-VOLTAGE BUFFERS

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United States of America Patent

APP PUB NO 20090040668A1
SERIAL NO

11837306

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Abstract

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An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.

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Patent Owner(s)

Patent OwnerAddress
TRANSPACIFIC IP LTDROOM 1402 14F NO 205 DUNHUA N ROAD SONGSHAN DISTRICT TAIPEI CITY 105 R O C

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Zi-Ping Hsinchu, TW 19 176
Jiang, Hsin-Chin Hsinchu, TW 31 299
Ker, Ming-Dao Hsinchu, TW 2 21

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  • 12 Citation Count
  • H02H Class
  • 58.19 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1318682261066523301 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 90100 +0102030405060708090100110120130140150160170180190200

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