Systems and methods for reducing distortion in semiconductor based sampling systems
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United States of America Patent
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Issued Date -
Feb 12, 2009
app pub date -
Aug 9, 2007
filing date -
Aug 9, 2007
priority date (Note) -
Abandoned
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Abstract
Circuits and methods that improve the performance of electronic sampling systems are provided. Parasitic capacitance associated with bootstrap circuitry is reduced, thereby decreasing signal distortion caused by capacitive loading at the input of the sampling circuit. The impedance of a sampling semiconductor switch is maintained substantially constant during sample states, at least in part, by accounting for non-linear parasitic capacitances associated with a sampling switch control terminal in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.
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