METHOD AND APPARATUS FOR GENERATING FULLY DETAILED THREE-DIMENSIONAL ELECTRONIC PACKAGE AND PCB BOARD MODELS

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United States of America Patent

APP PUB NO 20090030660A1
SERIAL NO

11782393

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Abstract

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A process is provided, which includes receiving geometrical information for a plurality of layers of an electronic structure within at least one output data file from an electronic structure design tool. At least one numerical analysis data file is created from the output data file, which contains the geometrical information and has a file structure compatible with a numerical analysis tool for characterizing the electronic structure. The numerical analysis tool is used to read the numerical analysis data file and generate a three-dimensional meshed geometric model of the electronic structure from the numerical analysis data file, wherein the model includes three-dimensional geometric models of each layer. The model can then be used, for example, to solve numerical thermal, mechanical or electrical equations that are applied to the model.

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Patent Owner(s)

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LSI LOGIC CORPORATION1621 BARBER LANE MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Celik, Zeki Sunnyvale, US 1 5
Mertol, Atila Cupertino, US 17 931

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