NON-VOLATILE DRAM WITH FLOATING GATE AND METHOD OF OPERATION
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United States of America Patent
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N/A
Issued Date -
Jan 15, 2009
app pub date -
Jul 12, 2007
filing date -
Jul 12, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from the first region. A body region of the first conductivity type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region. A control gate is capacitively coupled to the floating gate.
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Cited Art Landscape
Patent Citation Ranking
- 11 Citation Count
- H01L Class
- 41.79 % this patent is cited more than
- 16 Age