Method for Achieving Uniform Chemical Mechanical Polishing In Integrated Circuit Manufacturing
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United States of America Patent
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app pub date -
Jun 20, 2008
filing date -
May 9, 2006
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Abstract
A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile memory integrated circuit. A second film, which is a sacrificial film formed using a second material, such as silicon oxide, is then provided over the first film. Partial removal of the second film is carried out using chemical mechanical polishing until a portion of the first film is exposed using a first slurry that is selective to the first material. Thereafter, the remaining layer of the second film is removed, along with planarization of the surface, using a second slurry that is highly selective, i.e., has a selectivity of the first film to the second film that is greater than a predetermine value (e.g., 16:1).
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