LOW POWER-CONSUMPTION DATA PROCESSOR
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United States of America Patent
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Issued Date -
Dec 18, 2008
app pub date -
Mar 3, 2008
filing date -
Jun 12, 2007
priority date (Note) -
Abandoned
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Abstract
A low power-consumption data processor, wherein instruction decoding is performed on an instruction memory and an instruction register by an instruction decoding unit through an instruction bus, being characterized in that an instruction decoding circuit is disposed between the instruction register, a program counter and an arithmetic logic unit, wherein a new value in an instruction is transmitted on a new instruction bus (NIB) when the decoded result is an operation/jump/call instruction and, otherwise, the new value is transmitted on an original instruction bus (IB).
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