Semiconductor memory device and method of operation
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United States of America Patent
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Issued Date -
Dec 18, 2008
app pub date -
Jun 13, 2007
filing date -
Jun 13, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.
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