Semiconductor device with integrated trench lateral power MOSFETs and planar devices

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United States of America Patent

SERIAL NO

12149016

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Abstract

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Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

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Patent Owner(s)

Patent OwnerAddress
FUJI ELECTRIC SYSTEMS CO LTD11-2 OSAKI 1-CHOME SHINAGAWA-KU TOKYO 141-0032

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujishima, Naoto Nagano, JP 55 1150
Kitamura, Mutsumi Nagano, JP 23 267
Sugi, Akio Nagano, JP 18 269
Tabuchi, Katsuya Nagano, JP 8 111
Wakimoto, Setsuko Nagano, JP 15 124

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