Circuit structure for timer counter and electrical device using the same
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United States of America Patent
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Issued Date -
Dec 4, 2008
app pub date -
Jan 25, 2008
filing date -
Jun 1, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A circuit structure for a timer counter counting the cycles of the pulse width of a digital signal corresponding to a clock signal is provided, wherein the signal type of the digital signal is Non-return to zero code. The timer counter circuit structure includes a first counter module and a second counter module. The first counter module receives the digital signal and the clock signal and counts the cycles of the pulse width of the digital signal corresponding to the clock signal while the logic of the digital signal is high. The second counter module receives the inverted digital signal and the clock signal and counts the cycles of pulse width of the inverted digital signal corresponding to the clock signal while the logic of the inverted digital signal is low.
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