SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE
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United States of America Patent
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Issued Date -
Nov 27, 2008
app pub date -
May 23, 2007
filing date -
May 23, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises V.sub.S and thus drives V.sub.GS below local threshold even for over-erased transistors of the sector that have a V.sub.Goff de-assertion voltage applied to their control gates for purpose of turning those transistors off. In one embodiment, the variable source resistance is set to a second intermediate resistance value during a testing mode that tests the extent to which the corresponding sector has been over-erased. The results of the testing mode are then used to intelligently optimize the number of transistors that are simultaneously soft-programmed in that sector during each V.sub.t compaction cycle.
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