Method and circuit for stressing upper level interconnects in semiconductor devices
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United States of America Patent
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Issued Date -
Nov 20, 2008
app pub date -
May 15, 2007
filing date -
May 15, 2007
priority date (Note) -
Abandoned
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Abstract
A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein.
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