FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY
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United States of America Patent
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N/A
Issued Date -
N/A
app pub date -
Jul 29, 2008
filing date -
Jul 17, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
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Patent Citation Ranking
- 18 Citation Count
- G11C Class
- 40.95 % this patent is cited more than
- 17 Age