CURRENT MIRROR CIRCUIT
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United States of America Patent
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Issued Date -
Oct 23, 2008
app pub date -
Nov 23, 2007
filing date -
Nov 23, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention relates to a current mirror circuit (110) having a first transistor (112) and a second transistor (114), each of which have a control terminal (128, 136), formed particularly as a base or gate, and in each case two current terminals (124, 126, 132, 134), formed particularly as an emitter and collector or drain and source, whereby the control terminals (128, 136) of both transistors (112, 114) are connected to one another in an electrically conducting way at a connection node (140) and to a first current terminal (124, 126) of the first transistor (112) via a connecting line (150). It is provided according to the invention that the connecting line (150) is assigned bias means, provided for shifting an electric potential at the first current terminal (124) of the first transistor (112) relative to an electric potential of the connection node (140). Use in integrated circuits
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