THERMAL BONDING PROCESS FOR CHIP PACKAGING
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United States of America Patent
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app pub date -
Apr 3, 2007
filing date -
Apr 3, 2007
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Abstract
The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging.
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