Sample and Hold Circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Oct 9, 2008
app pub date -
Sep 28, 2005
filing date -
Sep 28, 2004
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The voltage produced by an input current (i.sub.n) is sampled (S1, S2, S3) and stored on the gate (46) of a Fet (T1). The stored gate voltage allows the FET to function as the reference current source of a current mirror (T2, T3) which generates an output current (i.sub.out) proportional to the sampled input current. The current mirror uses dual gate floating gate FETS (T2, T3) whose mirroring ratio can be finely adjusted by adjusting the bias voltages (V1, V2) applied to their auxiliary gate electrodes (425,435).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully