PROCESS OF FILLING DEEP VIAS FOR 3-D INTEGRATION OF SUBSTRATES
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United States of America Patent
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Issued Date -
Oct 2, 2008
app pub date -
Mar 30, 2007
filing date -
Mar 30, 2007
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Abandoned
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Abstract
A method for filling defect-free conductive material in deep vias or cavities in semiconductor wafers in 3-D integration structures is provided. The process may be performed in at least two steps for depositing the conductive material, including a first deposition step that partially fills the cavity with the conductive material and forms a conformal layer, which may also reduce the depth and width of the cavity, and a second deposition step that completely fills the same conductive material into the space defined by the conformal layer.
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