Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch
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United States of America Patent
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Mar 9, 2010
Grant Date -
Sep 4, 2008
app pub date -
Feb 19, 2008
filing date -
Apr 26, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
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