ON-CHIP IMPEDANCE MATCHING USING A VARIABLE CAPACITOR
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United States of America Patent
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Issued Date -
Sep 4, 2008
app pub date -
Mar 1, 2007
filing date -
Mar 1, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system and a method for on-chip impedance matching, of at least two ports: an output source and an input load. The system includes an on-chip integrated impedance matching circuit (IMC) that comprises: at least one variable capacitor; a control unit that enables tuning of the variable capacitor, receiving and transmitting of signals and processing of signals; and at least one peak detector that enables detection of signal peaks (SP). Control unit enables determining of a substantially optimal signal peak and tuning of the variable capacitor to a substantially optimal capacitance that is corresponding to the said optimal signal peak. The highest signal peak provides the substantially optimal impedance matching between the ports.
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