Voltage regulator
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United States of America Patent
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N/A
Issued Date -
Jul 31, 2008
app pub date -
Nov 29, 2007
filing date -
Dec 8, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A voltage regulator according to the present invention is operated stably. Regardless of a condition of a load (25), a variation in drain voltage of a PMOS transistor (34) is made equal to a variation in output voltage (Vout) at an output terminal of the voltage regulator. Then, a variation in voltage which is equal to the variation in output voltage (Vout) at the output terminal which is caused by a change of the condition of the load (25) is fed back to an error amplifier (70), so a gain of a signal for phase compensation which is fed back to the error amplifier (70) is determined based on the output voltage (Vout). Therefore, even when the condition of the load (25) changes, the behavior of phase compensation is correct.
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