CLOCK GENERATING CIRCUIT AND METHOD THEREOF
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United States of America Patent
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Issued Date -
Jul 24, 2008
app pub date -
Jun 4, 2007
filing date -
Jan 23, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A clock generating circuit and method therefor are provided, which includes a control unit, a first oscillating module, a second oscillating module, a status control unit, and a multiplexer. The control unit is used for outputting a first control signal and a second control signal so as to drive the first oscillating module and the second oscillating module to generate or stop from a first clock signal and a second signal to the multiplexer. The status control unit is used for judging whether the second clock signal approaches a stable state, for controlling the multiplexer to output selectively the first clock signal or the second clock signal so as to maintain the stable state of a clock outputting by the multiplexer for all the time
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