Power-on reset circuit
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United States of America Patent
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Issued Date -
May 8, 2008
app pub date -
Oct 19, 2006
filing date -
Oct 19, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The power-on reset circuit of the present invention includes a buffer, a delay circuit connected to the buffer and a constant current source circuit connected to the delay circuit. The delay circuit is made up by two capacitors, two resistors, an NMOS transistor and a PMOS transistor. The two capacitors are respectively made up by an NMOS transistor and a PMOS transistor. A current of the constant current source circuit changes along with a voltage variation of a DC power supply to respectively provide two constant voltage reference sources to the corresponding gates of the NMOS transistor and the PMOS transistor of the delay circuit. The NMOS transistor and the PMOS transistor of the constant current source circuit and the NMOS transistor and the PMOS transistor of the delay circuit form a mirroring circuit.
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