PHASE LOCKED LOOP HAVING CONTINUOUS BANK CALIBRATION UNIT AND METHOD OF PREVENTING UNLOCKING OF PLL
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United States of America Patent
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Issued Date -
Apr 17, 2008
app pub date -
Oct 8, 2007
filing date -
Oct 12, 2006
priority date (Note) -
Abandoned
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Abstract
A phase locked loop (PLL) having a continuous bank calibration unit and a method of preventing unlocking of the PLL are provided. The PLL includes a main circuit, a voltage controlled oscillator (VCO), and a continuous bank calibration unit. The main circuit outputs a control voltage in response to an external clock signal and an oscillating signal. The VCO outputs the oscillating signal in response to the control voltage and the bank calibration signal. The continuous bank calibration unit compares the received control voltage with a window voltage having at least two comparison values to output the bank calibration signal. In the PLL having a continuous bank calibration unit, although the control voltage varies with external factors such as temperature, the bank of the VCO is immediately and suitably calibrated to prevent unlocking of the PLL, so that it is possible to Improve an output characteristic of the VCO.
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