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Abstract

A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that electrical interaction between the access device and the memory device is characterized by a sensitivity parameter having a value within a predetermined range for a sub-threshold voltage applied to a gate electrode of the access device. To achieve good scalability of the dual-gate memory cells, the semiconductor layer between the memory device gate and access device gate can be thinned. This results in a larger sensitivity parameter but this parameter is still small enough to avoid memory charge disturbs. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

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First Claim