ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE
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United States of America Patent
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N/A
Issued Date -
Feb 28, 2008
app pub date -
Jul 27, 2007
filing date -
Jul 28, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.
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