Microprocessor and Method of Instruction Alignment
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United States of America Patent
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Issued Date -
Jan 31, 2008
app pub date -
May 18, 2005
filing date -
May 27, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Therefore, a microprocessor for processing instructions is provided. Said microprocessor comprises a cache for caching instructions and/or data to be processed, which are arranged in cache words, and an alignment unit for aligning instructions to predetermined positions with regard to cache word boundaries of said cache by introducing padding bytes (padd1, padd2). At least one of said padding bytes (padd1, padd2) include static data, which are required within the processing of one of said instructions. Accordingly, the padding bytes which are required for the alignment of the instructions, can be utilized for data which is needed during the processing of the instruction such that these bytes are not wasted and the available storage capacity is efficiently used.
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