Method for the functional verification of at least one analog circuit block
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United States of America Patent
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Issued Date -
Jan 24, 2008
app pub date -
Jul 5, 2007
filing date -
Jul 5, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method is provided for verifying at least one circuit block or a circuit, which has at least two interconnected circuit blocks, in which for digitalizing the signal values, in a first verification step, at least one line is supplied with the signal at the input of the block, in a second step, the signal at the output of the block is checked for a predefined target function, in a third step, a data value is assigned to the circuit block when the predefined target function is achieved and another data value when the predefined target value is not achieved, and in a fourth step, the assigned data value is stored with an indication of the circuit block supplied with a signal.
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