METHOD AND SYSTEM FOR SEALING PACKAGES FOR OPTICS
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United States of America Patent
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app pub date -
Sep 12, 2007
filing date -
Oct 24, 2003
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Abandoned
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Abstract
A system for wafer-level packaging of a plurality of MEMS devices includes a substrate having a plurality of individual chips. Each of the plurality of individual chips includes a plurality of MEMS devices and each of the plurality of individual chips is arranged in a spatial manner as a first array configuration. The system also includes a transparent member of a predetermined thickness. The transparent member includes a transparent substrate of a first thickness having a bonding surface joined to a bonding surface of a standoff substrate of a second thickness. The standoff substrate defines a plurality of recessed regions arranged in a spatial manner as a second array configuration. The system further includes a sealed interface between the standoff substrate and the substrate. The sealed interface is adapted to enclose each of the plurality of individual chips within one of the plurality of recessed regions.
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