PIPELINED SEMICONDUCTOR MEMORIES AND SYSTEMS
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United States of America Patent
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app pub date -
Jun 29, 2007
filing date -
Jun 2, 2003
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Abstract
The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.
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