VIRTUAL TESTER ARCHITECTURE
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United States of America Patent
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Issued Date -
Dec 20, 2007
app pub date -
May 31, 2006
filing date -
May 31, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A virtual tester, for testing a device logic simulator, includes multiple virtual instruments that generate stimulus messages for delivery to the device logic simulator and for receiving response messages generated by the device logic simulator. Each virtual instrument models a corresponding hardware test instrument and comprises a concrete instrument model that behaves in a manner corresponding to the corresponding hardware test instrument and also comprises an abstract interface that is independent of the behavior of the corresponding hardware test instrument. At least one virtual instrument generates sync messages for coordinating operation of the virtual instruments. A virtual tester engine receives the sync messages and executes an algorithm in which the virtual tester engine cyclically identifies sync messages that pertain to a current operating cycle, communicates sync messages to each virtual instrument, validates sync messages based on responses by the virtual instruments to the sync messages and communicates the validated sync messages to each virtual instrument. A virtual instrument that is specified by a validated sync message performs a test activity based on the validated sync message and a user test program.
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