Current Mirror Arrangement
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United States of America Patent
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N/A
Issued Date -
Dec 20, 2007
app pub date -
Aug 31, 2005
filing date -
Sep 1, 2004
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A current mirror arrangement is specified in which two current mirror transistors (2, 3) form a current mirror. Two cascode transistors (11, 12) are connected up to the two current mirror transistors (2, 3) to form a cascode stage. The cascode transistors (11, 12) in each case comprise a plurality of partial transistors (13, 14, 15; 16, 17, 18) connected up to one another in series with respect to their controlled paths. As a result it is possible to connect the connecting node of the current mirror transistors to a connecting node between two partial transistors (14, 15). This in turn brings about an increase in the input voltage range for a current source (4) that provides an input current for the current mirror.
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