HIGH BANDWIDTH, HIGH CAPACITY LOOK-UP TABLE IMPLEMENTATION IN DYNAMIC RANDOM ACCESS MEMORY
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United States of America Patent
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Issued Date -
Dec 13, 2007
app pub date -
Dec 14, 2006
filing date -
Jun 13, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Fixed-cycle latency accesses to a dynamic random access memory (DRAM) are designed for read and write operations in a packet processor. In one embodiment, the DRAM is partitioned to a number of banks, and the allocation of information to each bank to be stored in the DRAM is matched to the different types of information to be looked up. In one implementation, accesses to the banks can be interleaved, such that the access latencies of the banks can be overlapped through pipelining. Using this arrangement, near 100% bandwidth utilization may be achieved over a burst of read or write accesses.
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