Phase-Slipping Phase-Locked Loop
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United States of America Patent
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Issued Date -
Dec 13, 2007
app pub date -
Mar 20, 2007
filing date -
Mar 21, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A phase-slipping phase-locked loop which generates an output signal whose frequency is a non-integer multiple of a reference frequency. The PLL has a first input for receiving a first binary value i which specifies an integer portion of the frequency multiplier, and a second input for receiving a second binary value f which specifies a fractional portion of the frequency multiplier. A multi-phase VCO has a plurality v of outputs on equal phase shifted spacing. The phase slipping is applied every i cycles, and the second binary value f specifies a phase slip stride, such that the frequency multiplier equals i+f/v.
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