Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing
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United States of America Patent
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Issued Date -
Dec 6, 2007
app pub date -
Jun 1, 2006
filing date -
Jun 1, 2006
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Abstract
A method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing includes depositing a gate polysilicon layer on a semiconductor substrate which has a field oxide isolation structure, and then performing a polysilicon chemical-mechanical polishing after a gate polysilicon layer is deposited in order to smooth the uneven polysilicon surface resulting from the field oxide isolation structure so as to lessen the next lithography process fault because of the non-flatness.
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