Techniques to reduce circuit non-linear distortion
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United States of America Patent
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Issued Date -
Dec 6, 2007
app pub date -
Jun 2, 2006
filing date -
Jun 2, 2006
priority date (Note) -
Abandoned
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Abstract
An embodiment of the present invention provides a method, comprising minimizing non-linear distortion effects in a circuit by applying tuning voltages within a predetermined voltage range to a plurality of oppositely oriented tunable capacitors within the circuit, thereby reducing the non-linear distortion effects. An embodiment of the present invention may further comprise applying an RF voltage within specified limits and wherein the predetermined voltage range may be determined so the combined capacitance of the plurality of tunable capacitors within the circuit remains essentially constant. Further, the predetermined voltage range may be derived by a CV curve that results in a constant total capacitance with no non-linear distortion.
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