Non-volatile flash memory structure and method for operating the same
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United States of America Patent
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Issued Date -
Oct 18, 2007
app pub date -
Apr 14, 2006
filing date -
Apr 14, 2006
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Abandoned
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Abstract
A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.
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