Semiconductor integrated circuit device and method of testing same
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United States of America Patent
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Apr 13, 2010
Grant Date -
Sep 27, 2007
app pub date -
Mar 8, 2007
filing date -
Mar 14, 2006
priority date (Note) -
Expired
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Abstract
Disclosed is a circuit in which for conducting the scan path test, test clock terminals are provided in a number smaller than that of user clock domains, and a test clock control circuits on respective test clock lines to control whether the pulses of the test clock are propagated or blocked.
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