Partial cascode delay locked loop architecture
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United States of America Patent
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Issued Date -
Sep 20, 2007
app pub date -
Mar 17, 2006
filing date -
Mar 17, 2006
priority date (Note) -
Abandoned
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Abstract
Various embodiments for a partial cascode delay locked loop architecture are described. In one embodiment, an apparatus may include a delay locked loop circuit having a plurality of partial cascode circuits. The plurality of partial cascode circuits may be arranged to reduce phase noise from a ground power supply voltage and a power supply voltage. Other embodiments are described and claimed.
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