Method of Operation of a Microprocessor
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United States of America Patent
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N/A
Issued Date -
Aug 23, 2007
app pub date -
Dec 1, 2006
filing date -
Dec 3, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention relates to a microprocessor and a method of operation thereof. More particularly this invention relates to a microprocessor, having at least three pipeline execution units which operate in lockstep. In an embodiment, the method of operation of a microprocessor accounts for the occurrence of transient faults or Single Event Upsets in one of its pipeline execution units such that their occurrence is unlikely to result in failure of the microprocessor as a whole.
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