Reverse polish notation processing device, and electronic integrated circuit including such a processing device
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United States of America Patent
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Issued Date -
Aug 16, 2007
app pub date -
Jan 24, 2007
filing date -
Jan 24, 2006
priority date (Note) -
Abandoned
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Abstract
The disclosure relates to a reverse Polish notation processing device, allowing execution of a set of instructions wherein each instruction comprises N operands at most, where N.gtoreq.1. The device implements management of a stack whose size is variable. Such a device includes: a storage device including a random access memory and a cache memory; a stack pointer managing device for managing a stack pointer; and a contents managing device for managing the contents of the stages of the stack, according to said stack pointer. For each of the first N stages of the stack, the content of said stage is stored in the cache memory, and for each of the other stages of the stack, the content of said stage is stored in the random access memory; allowing to manage content overflows from the cache memory towards the random access memory, and vice-versa.
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