Stacked chip packaging structure
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United States of America Patent
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N/A
Issued Date -
Jul 5, 2007
app pub date -
Nov 3, 2006
filing date -
Jan 5, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A stacked chip packaging structure (10) includes a substrate (20), a first chip (40), a second chip (70), and a cover (80). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires (50a). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires (50b). The cover is mounted above the second chip and the wires connected with the second chip. The mounting of the second chip and the cover in such a manner is facilitated through the use of an adhesive/glue (60a, 60b) that is able to function both as an adherent and as a spacer.
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