Flash memory cell and fabrication method thereof
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United States of America Patent
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Issued Date -
Jun 7, 2007
app pub date -
Dec 29, 2005
filing date -
Sep 20, 2005
priority date (Note) -
Abandoned
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Abstract
A flash memory cell transistor is presented that includes a stacked structure of successively formed tunnel oxide layer, floating gate, inter-gate insulating layer and control gate on a semiconductor substrate, an insulating thin film formed on a first sidewall of the stacked structure, and an access gate formed on the first sidewall of the stacked structure while interposing the insulating thin film. A drain region is formed in a first region of the substrate in which the first region is exposed by the floating gate and a source region is formed in a second region of the substrate in which the second region is exposed by the access gate. The access gate overlaps, along the vertical direction of the stacked structure, the control gate and the floating gate.
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