Memory controller and method thereof
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United States of America Patent
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Issued Date -
May 31, 2007
app pub date -
Nov 30, 2006
filing date -
Nov 30, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A memory controller and method thereof are provided. The memory controller includes a control logic circuit, a phase locked loop (PLL) and a multiplexer. The PLL generates a plurality of phase clock signals according to a system clock signal. The phase clock signals have the same frequency with the system clock. The phase clock signals have different phase difference to each other. The multiplexer receives the phase clock signals under the control of the control logic circuit, then selects and outputs one of the phase clock signals to generate a selected phase clock signal.
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