High speed sigma delta device
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United States of America Patent
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Issued Date -
Mar 29, 2007
app pub date -
Sep 28, 2005
filing date -
Sep 28, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system and method are provided for a high speed sigma delta circuit operation including a sigma-delta analog to digital converter configured to receive an input signal and to output a single digital bit representative of that signal and any associated noise. Further included is a finite impulse response filter configured to accumulate a stream of digital bits from the ADC device within a shift register, to sum a coefficient of each bit, and weigh each bit in response to a corresponding bit in the shift register. Also included is a quantizing device for receiving the summation of the weighted bits of the FIR device and rendering a representative bit as output.
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