System and method for generating self-aligned clock signals for consecutive circuit operations
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United States of America Patent
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Issued Date -
Mar 29, 2007
app pub date -
Sep 28, 2005
filing date -
Sep 28, 2005
priority date (Note) -
Abandoned
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Abstract
A system and method of generating a clock signal are provided for driving a plurality of consecutive circuit phase operations. The method includes generating a clock signal, transmitting the clock signal to one circuit phase operation, and transmitting another clock signal to a previous circuit phase operation. A circuit configured according to the invention can clock a plurality of consecutive circuit phase operations with a single master clock, where each circuit phase generates a clock signal to clock a previous phase, obviating connections from a master clock to multiple phases.
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