Method for reducing substrate noise from penetrating noise sensitive circuits
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United States of America Patent
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Issued Date -
Feb 22, 2007
app pub date -
May 23, 2006
filing date -
May 23, 2005
priority date (Note) -
Abandoned
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Abstract
A CMOS device includes a p-type substrate and an isolated PWell region. An isolation region has an NWell region abutting a perimeter of the PWell region. The isolation region includes a DNWell region positioned below the PWell region and an NWell region. The NWell region forms a sidewall of a tub and the DNWell region forms a bottom of the tub. The tub is an n-type region that physically and electrically isolates an enclosed PWell region from the p-type substrate. A NTN region is formed in the p-type substrate and at least partially abuts an outer perimeter of the NWell region. The NTN region is defined as a non-PWell and a non-NWell region. The NTN region enhances electrical isolation of the circuits inside the PWell region from circuits outside of the PWell region. In one embodiment, the high-frequency performance of an NMOSFET inside the isolated PWell is improved because of the reduced sidewall capacitance with the NTN region.
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