Measuring alignment between a wafer chuck and polishing/plating receptacle
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United States of America Patent
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Issued Date -
Feb 22, 2007
app pub date -
Dec 9, 2003
filing date -
Dec 9, 2003
priority date (Note) -
Abandoned
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Abstract
An apparatus for electropolishing and/or electroplating metal layers on a semiconductor wafer includes a receptacle having a plurality of section walls. The apparatus includes a wafer chuck configured to hold the semiconductor wafer and to position the semiconductor wafer within the receptacle with a surface of the semiconductor wafer adjacent to top portions of the plurality of section walls. The apparatus also includes a first plurality of sensors configured to measure alignment between the center of one of the plurality of section walls to the center of the wafer chuck, and thus the center of the semiconductor wafer.
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