Method and system for reshaping metal wires in VLSI design
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Feb 8, 2007
app pub date -
Aug 8, 2005
filing date -
Aug 8, 2005
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A method and system for representing metal wires in Very Large Scale Integration (VLSI) circuit design in a simplified form. A pair of metal wires is considered at a time. A plurality of Piece Wise Linear (PWL) equations is created to represent sides each of the pair of metal wires. The plurality of PWL equations is used to determine an equivalent coupling capacitance of the pair of metal wires. The pair of metal wires is reshaped to form a pair of reshaped metal wires that are electrically equivalent.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully