Forgetful logic for artificial neural networks
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United States of America Patent
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Issued Date -
Jan 25, 2007
app pub date -
Mar 15, 2006
filing date -
Mar 15, 2005
priority date (Note) -
Abandoned
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Abstract
An embodiment includes a plurality of tangible electronic elements interconnected to form a forgetful latch. The forgetful latch includes a pass element operable to receive input pulses; a biasing element coupled to the pass element and operable to bias a storage node charged by at least one of the input pulses; and an inverter coupled to the biasing elements and operable to produce an output pulse that stretches the input pulses.
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